The present invention relates in general to integrated circuits and, more particularly, to sensing a common-mode voltage of a clocked differential amplifier.
Signal processing functions are often implemented more economically using digital rather than analog methods. For example, a wireless communication device such as a cellular telephone or pager often uses fewer external tuning components if a transmitted carrier signal is converted to digital data at an early stage in the communication device. A high frequency analog-to-digital converter (ADC) is used for converting the analog carrier signal to a digital data stream. A demodulated signal is computed from the digital data stream using a preprogrammed demodulation mathematical algorithm.
A typical high frequency ADC includes a plurality of parallel time-interleaved, pipelined ADC channels which sample the carrier signal at alternating time points and produce data words representative of the amplitude of the analog carrier signal at the time of the sample. The data words from each channel are interleaved to form the digital data stream. A low data error rate requires symmetry among the parallel channels, including carefully matched components and timing signals.
Analog signals are processed through each channel in a series of pipelined sample-and-hold stages. A clocked differential amplifier in each sample-and-hold stage processes an analog input signal to produce a residue signal that is clocked to the next stage using switched capacitors enabled on alternate clock phases. Control of common-mode voltages is needed to maintain the analog signals within the operating ranges of the differential amplifiers, which is provided by periodically refreshing the common-mode voltages to desired levels with a common-mode sensing circuit. However, prior art common-mode sensing circuits produce different loads at the outputs of the differential amplifiers during the alternate clock phases. The difference in loading results in output spurs in the differential amplifier frequency response, which produces data errors and incorrect demodulation of the carrier signal.
Hence, there is a need for a common-mode sensing circuit which reduces output spurs and data errors.